This invention relates to a semiconductor device of stacked gate structure, and more particularly to a nonvolatile semiconductor memory device in which data can be erased by applying an ultraviolet ray and a manufacturing method therefor. 2. Description of the related art including information disclosed under .sctn..sctn.1.97-1.99
In general, an ultraviolet erasable nonvolatile semiconductor memory device (EPROM) has a stacked gate structure of two polysilicon layers serving as a floating gate and a control gate which are formed one over the other. An insulation film provided between the two polysilicon layers and a metal wiring layer arranged over the double polysilicon layers is formed of laminated structure of a thermal oxide film and an SiO.sub.2 film (PSG film) having phosphorus of 1.times.10.sup.20 cm.sup.-3 doped therein. The PSG film melts in a heat treatment process (at about 950.degree. C. or more) effected at a later stage, and an uneven surface of the semiconductor substrate caused by the presence of the two polysilicon layers can be made flat by the melted PSG. The planarization makes it easy to pattern the metal wiring layer formed on the insulation film and effectively prevents occurrence of defects such as disconnection of wiring layers.
However with the scaling down of recent memory elements, the maximum permissible temperature in the heat treatment process for the planarization is lowered. For this reason, it becomes difficult to attain the planarization by causing the PSG film to melt. In order to solve the problem it is considered that an SiO.sub.2 film having boron and phosphorus (BPSG film) of more than 1.times.10.sup.20 cm.sup.-3 doped therein is used instead of the PSG film. The BPSG film has an advantage that the melting point is as low as 900.degree. C. or less, but it has a property of making the transmission of ultraviolet rays difficult. For this reason, in the case where the BPSG film is used in the ultraviolet erasable EPROM, the data erasing speed will be lowered.